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rdcu_ctrl.h

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  • rdcu_ctrl.h 9.55 KiB
    /**
     * @file   rdcu_ctrl.h
     * @author Armin Luntzer (armin.luntzer@univie.ac.at)
     * @date   2018
     *
     * @copyright GPLv2
     * This program is free software; you can redistribute it and/or modify it
     * under the terms and conditions of the GNU General Public License,
     * version 2, as published by the Free Software Foundation.
     *
     * This program is distributed in the hope it will be useful, but WITHOUT
     * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     * more details.
     *
     * @brief RMAP RDCU control library header file
     * @see FPGA Requirement Specification PLATO-IWF-PL-RS-005 Issue 0.6
     */
    
    #ifndef RDCU_CTRL_H
    #define RDCU_CTRL_H
    
    #include <stdint.h>
    
    
    /**
     * @brief local mirror of the RDCU registers
     */
    
    struct rdcu_mirror {
    	/* RDCU registers */
    	uint32_t fpga_version;			/* RDCU-FRS-FN-0522 */
    	uint32_t rdcu_status;			/* RDCU-FRS-FN-0532 */
    	uint32_t lvds_core_status;		/* RDCU-FRS-FN-0542 */
    	uint32_t spw_link_status;		/* RDCU-FRS-FN-0552 */
    	uint32_t spw_err_cntrs;			/* RDCU-FRS-FN-0562 */
    	uint32_t rmap_last_err;			/* RDCU-FRS-FN-0572 */
    	uint32_t rmap_no_reply_err_cntrs;	/* RDCU-FRS-FN-0582 */
    	uint32_t rmap_pckt_err_cntrs;		/* RDCU-FRS-FN-0592 */
    	uint32_t adc_values_1;			/* RDCU-FRS-FN-0602 */
    	uint32_t adc_values_2;
    	uint32_t adc_values_3;
    	uint32_t adc_values_4;
    	uint32_t adc_status;			/* RDCU-FRS-FN-0610 */
    	uint32_t compr_status;			/* RDCU-FRS-FN-0632 */
    	uint32_t rdcu_reset;			/* RDCU-FRS-FN-0662 */
    	uint32_t spw_link_ctrl;			/* RDCU-FRS-FN-0672 */
    	uint32_t lvds_ctrl;			/* RDCU-FRS-FN-0682 */
    	uint32_t core_ctrl;			/* RDCU-FRS-FN-0692 */
    	uint32_t adc_ctrl;			/* RDCU-FRS-FN-0712 */
    	uint32_t compr_ctrl;			/* RDCU-FRS-FN-0732 */
    
    	/* Data Compressor registers */
    	uint32_t compressor_param1;		/* RDCU-FRS-FN-0772 */
    	uint32_t compressor_param2;		/* RDCU-FRS-FN-0782 */
    	uint32_t adaptive_param1;		/* RDCU-FRS-FN-0792 */
    	uint32_t adaptive_param2;		/* RDCU-FRS-FN-0802 */
    	uint32_t data_start_addr;		/* RDCU-FRS-FN-0812 */
    	uint32_t model_start_addr;		/* RDCU-FRS-FN-0822 */
    	uint32_t num_samples;			/* RDCU-FRS-FN-0832 */
    	uint32_t new_model_start_addr;		/* RDCU-FRS-FN-0842 */
    	uint32_t compr_data_buf_start_addr;	/* RDCU-FRS-FN-0852 */
    	uint32_t compr_data_buf_len;		/* RDCU-FRS-FN-0862 */
    
    	uint32_t used_param1;			/* RDCU-FRS-FN-0892 */
    	uint32_t used_param2;			/* RDCU-FRS-FN-0902 */
    	uint32_t compr_data_start_addr;		/* RDCU-FRS-FN-0912 */
    	uint32_t compr_data_size;		/* RDCU-FRS-FN-0922 */
    	uint32_t compr_data_adaptive_1_size;	/* RDCU-FRS-FN-0932 */
    	uint32_t compr_data_adaptive_2_size;	/* RDCU-FRS-FN-0942 */