From 5ad7afa6d06a48987381c3891ef0630dc80fd0fb Mon Sep 17 00:00:00 2001
From: Marko Mecina <marko.mecina@univie.ac.at>
Date: Tue, 15 Nov 2022 12:31:47 +0100
Subject: [PATCH] update IASW upload script

---
 Ccs/scripts/upload_IASW.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Ccs/scripts/upload_IASW.py b/Ccs/scripts/upload_IASW.py
index f691fc4..5114e05 100644
--- a/Ccs/scripts/upload_IASW.py
+++ b/Ccs/scripts/upload_IASW.py
@@ -5,7 +5,7 @@ binary = '/path/to/binary'  # IASW binary
 srecfile = '/path/to/srec'  # SREC filename
 start_addr = 0x60040000  # start address of IASW in RAM
 
-cfl.source_to_srec(binary, srecfile, start_addr)
+cfl.source_to_srec(binary, srecfile, start_addr, skip_bytes=0)
 
 # upload the SREC content to DPU
 memid = 'MEM_WR_MRAM'  # memory ID, 'DPU_MRAM' or 'MEM_WR_MRAM', depending on whether DBS or IASW S6 is used
-- 
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