/src/cmp_tool/lib/rdcu_compress/rdcu_cmd.h
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1 | | /** |
2 | | * @file rdcu_cmd.h |
3 | | * @author Armin Luntzer (armin.luntzer@univie.ac.at) |
4 | | * @date 2018 |
5 | | * |
6 | | * @copyright GPLv2 |
7 | | * This program is free software; you can redistribute it and/or modify it |
8 | | * under the terms and conditions of the GNU General Public License, |
9 | | * version 2, as published by the Free Software Foundation. |
10 | | * |
11 | | * This program is distributed in the hope it will be useful, but WITHOUT |
12 | | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
13 | | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
14 | | * more details. |
15 | | * |
16 | | * @brief RMAP RDCU RMAP command library header file |
17 | | * @see FPGA Requirement Specification PLATO-IWF-PL-RS-005 Issue 0.6 |
18 | | */ |
19 | | |
20 | | #ifndef RDCU_CMD_H |
21 | | #define RDCU_CMD_H |
22 | | |
23 | | #include <stdint.h> |
24 | | |
25 | | /* readable RDCU register addresses (RDCU-FRS-FN-0284) */ |
26 | 0 | #define FPGA_VERSION 0x10000000UL |
27 | 0 | #define RDCU_STATUS 0x10000004UL |
28 | 0 | #define LVDS_CORE_STATUS 0x10000008UL |
29 | 0 | #define SPW_LINK_STATUS 0x1000000CUL |
30 | 0 | #define SPW_ERR_CNTRS 0x10000010UL |
31 | 0 | #define RMAP_LAST_ERR 0x10000014UL |
32 | 0 | #define RMAP_NO_REPLY_ERR_CNTRS 0x10000018UL |
33 | 0 | #define RMAP_PCKT_ERR_CNTRS 0x1000001CUL |
34 | 0 | #define ADC_VALUES_1 0x10000020UL |
35 | 0 | #define ADC_VALUES_2 0x10000024UL |
36 | 0 | #define ADC_VALUES_3 0x10000028UL |
37 | 0 | #define ADC_VALUES_4 0x1000002CUL |
38 | 0 | #define ADC_STATUS 0x10000030UL |
39 | | /* spare: 0x10000034UL */ |
40 | 0 | #define COMPR_STATUS 0x10000038UL |
41 | | /* spare: 0x1000003CUL */ |
42 | | |
43 | | /* writeable RDCU register addresses (RDCU-FRS-FN-0284) */ |
44 | 0 | #define RDCU_RESET 0x10000040UL |
45 | 0 | #define SPW_LINK_CTRL 0x10000044UL |
46 | 0 | #define LVDS_CTRL 0x10000048UL |
47 | 0 | #define CORE_CTRL 0x1000004CUL |
48 | 0 | #define ADC_CTRL 0x10000050UL |
49 | | /* spare: 0x10000054UL */ |
50 | 0 | #define COMPR_CTRL 0x10000058UL |
51 | | /* spare: 0x1000005CUL */ |
52 | | |
53 | | |
54 | | |
55 | | /* writeable Data Compressor register addresses (RDCU-FRS-FN-0288) */ |
56 | 0 | #define COMPR_PARAM_1 0x11000000UL |
57 | 0 | #define COMPR_PARAM_2 0x11000004UL |
58 | 0 | #define ADAPTIVE_PARAM_1 0x11000008UL |
59 | 0 | #define ADAPTIVE_PARAM_2 0x1100000CUL |
60 | 0 | #define DATA_START_ADDR 0x11000010UL |
61 | 0 | #define MODEL_START_ADDR 0x11000014UL |
62 | 0 | #define NUM_SAMPLES 0x11000018UL |
63 | 0 | #define UPDATED_MODEL_START_ADDR 0x1100001CUL |
64 | 0 | #define COMPR_DATA_BUF_START_ADDR 0x11000020UL |
65 | 0 | #define COMPR_DATA_BUF_LEN 0x11000024UL |
66 | | /* spare: 0x11000028UL */ |
67 | | /* spare: 0x1100002CUL */ |
68 | | |
69 | | /* readable Data Compressor register addresses (RDCU-FRS-FN-0288) */ |
70 | 0 | #define USED_COMPR_PARAM_1 0x11000030UL |
71 | 0 | #define USED_COMPR_PARAM_2 0x11000034UL |
72 | 0 | #define COMPR_DATA_START_ADDR 0x11000038UL |
73 | 0 | #define COMPR_DATA_SIZE 0x1100003CUL |
74 | 0 | #define COMPR_DATA_ADAPTIVE_1_SIZE 0x11000040UL |
75 | 0 | #define COMPR_DATA_ADAPTIVE_2_SIZE 0x11000044UL |
76 | 0 | #define COMPR_ERROR 0x11000048UL |
77 | 0 | #define USED_UPDATED_MODEL_START_ADDR 0x1100004CUL |
78 | 0 | #define USED_NUMBER_OF_SAMPLES 0x11000050UL |
79 | | /* spare: 0x11000054UL */ |
80 | | /* spare: 0x11000058UL */ |
81 | | /* spare: 0x1100005CUL */ |
82 | | |
83 | | |
84 | | /* writeable SRAM EDAC register addresses (RDCU-FRS-FN-0292) */ |
85 | 0 | #define SRAM_EDAC_CTRL 0x01000000UL |
86 | | /* spare: 0x01000004UL */ |
87 | | |
88 | | /* readable SRAM EDAC register addresses (RDCU-FRS-FN-0292) */ |
89 | 0 | #define SRAM_EDAC_STATUS 0x01000008UL |
90 | | /* spare: 0x0100000CUL */ |
91 | | |
92 | | /* SRAM address range (RDCU-FRS-FN-0280) */ |
93 | 204 | #define RDCU_SRAM_START 0x00000000UL |
94 | 694 | #define RDCU_SRAM_END 0x007FFFFFUL |
95 | 136 | #define RDCU_SRAM_SIZE (RDCU_SRAM_END - RDCU_SRAM_START + 1UL) |
96 | | |
97 | | |
98 | | |
99 | | |
100 | | int rdcu_read_cmd_register(uint16_t trans_id, uint8_t *cmd, uint32_t addr); |
101 | | int rdcu_write_cmd_register(uint16_t trans_id, uint8_t *cmd, uint32_t addr); |
102 | | |
103 | | int rdcu_write_cmd_data(uint16_t trans_id, uint8_t *cmd, |
104 | | uint32_t addr, uint32_t size); |
105 | | int rdcu_read_cmd_data(uint16_t trans_id, uint8_t *cmd, |
106 | | uint32_t addr, uint32_t size); |
107 | | |
108 | | |
109 | | /* RDCU read accessors */ |
110 | | int rdcu_read_cmd_fpga_version(uint16_t trans_id, uint8_t *cmd); |
111 | | int rdcu_read_cmd_rdcu_status(uint16_t trans_id, uint8_t *cmd); |
112 | | int rdcu_read_cmd_lvds_core_status(uint16_t trans_id, uint8_t *cmd); |
113 | | int rdcu_read_cmd_spw_link_status(uint16_t trans_id, uint8_t *cmd); |
114 | | int rdcu_read_cmd_spw_err_cntrs(uint16_t trans_id, uint8_t *cmd); |
115 | | int rdcu_read_cmd_rmap_last_err(uint16_t trans_id, uint8_t *cmd); |
116 | | int rdcu_read_cmd_rmap_no_reply_err_cntrs(uint16_t trans_id, uint8_t *cmd); |
117 | | int rdcu_read_cmd_rmap_pckt_err_cntrs(uint16_t trans_id, uint8_t *cmd); |
118 | | int rdcu_read_cmd_adc_values_1(uint16_t trans_id, uint8_t *cmd); |
119 | | int rdcu_read_cmd_adc_values_2(uint16_t trans_id, uint8_t *cmd); |
120 | | int rdcu_read_cmd_adc_values_3(uint16_t trans_id, uint8_t *cmd); |
121 | | int rdcu_read_cmd_adc_values_4(uint16_t trans_id, uint8_t *cmd); |
122 | | int rdcu_read_cmd_adc_status(uint16_t trans_id, uint8_t *cmd); |
123 | | int rdcu_read_cmd_compr_status(uint16_t trans_id, uint8_t *cmd); |
124 | | |
125 | | /* RDCU read accessors */ |
126 | | int rdcu_write_cmd_rdcu_reset(uint16_t trans_id, uint8_t *cmd); |
127 | | int rdcu_write_cmd_spw_link_ctrl(uint16_t trans_id, uint8_t *cmd); |
128 | | int rdcu_write_cmd_lvds_ctrl(uint16_t trans_id, uint8_t *cmd); |
129 | | int rdcu_write_cmd_core_ctrl(uint16_t trans_id, uint8_t *cmd); |
130 | | int rdcu_write_cmd_adc_ctrl(uint16_t trans_id, uint8_t *cmd); |
131 | | int rdcu_write_cmd_compr_ctrl(uint16_t trans_id, uint8_t *cmd); |
132 | | |
133 | | /* Data Compressor write accessors */ |
134 | | int rdcu_write_cmd_compressor_param1(uint16_t trans_id, uint8_t *cmd); |
135 | | int rdcu_write_cmd_compressor_param2(uint16_t trans_id, uint8_t *cmd); |
136 | | int rdcu_write_cmd_adaptive_param1(uint16_t trans_id, uint8_t *cmd); |
137 | | int rdcu_write_cmd_adaptive_param2(uint16_t trans_id, uint8_t *cmd); |
138 | | int rdcu_write_cmd_data_start_addr(uint16_t trans_id, uint8_t *cmd); |
139 | | int rdcu_write_cmd_model_start_addr(uint16_t trans_id, uint8_t *cmd); |
140 | | int rdcu_write_cmd_num_samples(uint16_t trans_id, uint8_t *cmd); |
141 | | int rdcu_write_cmd_new_model_start_addr(uint16_t trans_id, uint8_t *cmd); |
142 | | int rdcu_write_cmd_compr_data_buf_start_addr(uint16_t trans_id, uint8_t *cmd); |
143 | | int rdcu_write_cmd_compr_data_buf_len(uint16_t trans_id, uint8_t *cmd); |
144 | | |
145 | | /* Data Compressor read accessors */ |
146 | | int rdcu_read_cmd_used_param1(uint16_t trans_id, uint8_t *cmd); |
147 | | int rdcu_read_cmd_used_param2(uint16_t trans_id, uint8_t *cmd); |
148 | | int rdcu_read_cmd_compr_data_start_addr(uint16_t trans_id, uint8_t *cmd); |
149 | | int rdcu_read_cmd_compr_data_size(uint16_t trans_id, uint8_t *cmd); |
150 | | int rdcu_read_cmd_compr_data_adaptive_1_size(uint16_t trans_id, uint8_t *cmd); |
151 | | int rdcu_read_cmd_compr_data_adaptive_2_size(uint16_t trans_id, uint8_t *cmd); |
152 | | int rdcu_read_cmd_compr_error(uint16_t trans_id, uint8_t *cmd); |
153 | | int rdcu_read_cmd_new_model_addr_used(uint16_t trans_id, uint8_t *cmd); |
154 | | int rdcu_read_cmd_samples_used(uint16_t trans_id, uint8_t *cmd); |
155 | | |
156 | | |
157 | | /* SRAM EDAC read accessors */ |
158 | | int rdcu_read_cmd_sram_edac_status(uint16_t trans_id, uint8_t *cmd); |
159 | | |
160 | | /* SRAM EDAC write accessors */ |
161 | | int rdcu_write_cmd_sram_edac_ctrl(uint16_t trans_id, uint8_t *cmd); |
162 | | |
163 | | #endif /* RDCU_CMD_H */ |