Coverage Report

Created: 2025-06-15 00:57

/src/cmp_tool/lib/rdcu_compress/rdcu_cmd.h
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Source (jump to first uncovered line)
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/**
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 * @file   rdcu_cmd.h
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 * @author Armin Luntzer (armin.luntzer@univie.ac.at)
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 * @date   2018
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 *
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 * @copyright GPLv2
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * @brief RMAP RDCU RMAP command library header file
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 * @see FPGA Requirement Specification PLATO-IWF-PL-RS-005 Issue 0.6
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 */
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#ifndef RDCU_CMD_H
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#define RDCU_CMD_H
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#include <stdint.h>
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/* readable RDCU register addresses (RDCU-FRS-FN-0284) */
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#define FPGA_VERSION      0x10000000UL
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#define RDCU_STATUS     0x10000004UL
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#define LVDS_CORE_STATUS    0x10000008UL
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#define SPW_LINK_STATUS     0x1000000CUL
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#define SPW_ERR_CNTRS     0x10000010UL
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#define RMAP_LAST_ERR     0x10000014UL
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#define RMAP_NO_REPLY_ERR_CNTRS   0x10000018UL
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#define RMAP_PCKT_ERR_CNTRS   0x1000001CUL
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#define ADC_VALUES_1      0x10000020UL
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#define ADC_VALUES_2      0x10000024UL
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#define ADC_VALUES_3      0x10000028UL
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#define ADC_VALUES_4      0x1000002CUL
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#define ADC_STATUS      0x10000030UL
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/* spare: 0x10000034UL */
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#define COMPR_STATUS      0x10000038UL
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/* spare: 0x1000003CUL */
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/* writeable RDCU register addresses (RDCU-FRS-FN-0284) */
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#define RDCU_RESET      0x10000040UL
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#define SPW_LINK_CTRL     0x10000044UL
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#define LVDS_CTRL     0x10000048UL
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#define CORE_CTRL     0x1000004CUL
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#define ADC_CTRL      0x10000050UL
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/* spare: 0x10000054UL */
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#define COMPR_CTRL      0x10000058UL
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/* spare: 0x1000005CUL */
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/* writeable Data Compressor register addresses (RDCU-FRS-FN-0288) */
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#define COMPR_PARAM_1     0x11000000UL
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#define COMPR_PARAM_2     0x11000004UL
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#define ADAPTIVE_PARAM_1    0x11000008UL
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#define ADAPTIVE_PARAM_2    0x1100000CUL
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#define DATA_START_ADDR     0x11000010UL
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#define MODEL_START_ADDR    0x11000014UL
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#define NUM_SAMPLES     0x11000018UL
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#define UPDATED_MODEL_START_ADDR  0x1100001CUL
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#define COMPR_DATA_BUF_START_ADDR 0x11000020UL
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#define COMPR_DATA_BUF_LEN    0x11000024UL
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/* spare: 0x11000028UL */
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/* spare: 0x1100002CUL */
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/* readable Data Compressor register addresses (RDCU-FRS-FN-0288) */
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#define USED_COMPR_PARAM_1    0x11000030UL
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#define USED_COMPR_PARAM_2    0x11000034UL
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#define COMPR_DATA_START_ADDR   0x11000038UL
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#define COMPR_DATA_SIZE     0x1100003CUL
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#define COMPR_DATA_ADAPTIVE_1_SIZE  0x11000040UL
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#define COMPR_DATA_ADAPTIVE_2_SIZE  0x11000044UL
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#define COMPR_ERROR     0x11000048UL
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#define USED_UPDATED_MODEL_START_ADDR 0x1100004CUL
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#define USED_NUMBER_OF_SAMPLES    0x11000050UL
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/* spare: 0x11000054UL */
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/* spare: 0x11000058UL */
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/* spare: 0x1100005CUL */
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/* writeable SRAM EDAC register addresses (RDCU-FRS-FN-0292) */
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#define SRAM_EDAC_CTRL      0x01000000UL
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/* spare: 0x01000004UL */
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/* readable SRAM EDAC register addresses (RDCU-FRS-FN-0292) */
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#define SRAM_EDAC_STATUS    0x01000008UL
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/* spare: 0x0100000CUL */
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/* SRAM address range (RDCU-FRS-FN-0280) */
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#define RDCU_SRAM_START     0x00000000UL
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#define RDCU_SRAM_END     0x007FFFFFUL
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#define RDCU_SRAM_SIZE      (RDCU_SRAM_END - RDCU_SRAM_START + 1UL)
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int rdcu_read_cmd_register(uint16_t trans_id, uint8_t *cmd, uint32_t addr);
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int rdcu_write_cmd_register(uint16_t trans_id, uint8_t *cmd, uint32_t addr);
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int rdcu_write_cmd_data(uint16_t trans_id, uint8_t *cmd,
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      uint32_t addr, uint32_t size);
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int rdcu_read_cmd_data(uint16_t trans_id, uint8_t *cmd,
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           uint32_t addr, uint32_t size);
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/* RDCU read accessors */
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int rdcu_read_cmd_fpga_version(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_rdcu_status(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_lvds_core_status(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_spw_link_status(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_spw_err_cntrs(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_rmap_last_err(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_rmap_no_reply_err_cntrs(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_rmap_pckt_err_cntrs(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_adc_values_1(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_adc_values_2(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_adc_values_3(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_adc_values_4(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_adc_status(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_compr_status(uint16_t trans_id, uint8_t *cmd);
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/* RDCU read accessors */
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int rdcu_write_cmd_rdcu_reset(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_spw_link_ctrl(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_lvds_ctrl(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_core_ctrl(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_adc_ctrl(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_compr_ctrl(uint16_t trans_id, uint8_t *cmd);
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/* Data Compressor write accessors */
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int rdcu_write_cmd_compressor_param1(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_compressor_param2(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_adaptive_param1(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_adaptive_param2(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_data_start_addr(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_model_start_addr(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_num_samples(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_new_model_start_addr(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_compr_data_buf_start_addr(uint16_t trans_id, uint8_t *cmd);
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int rdcu_write_cmd_compr_data_buf_len(uint16_t trans_id, uint8_t *cmd);
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/* Data Compressor read accessors */
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int rdcu_read_cmd_used_param1(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_used_param2(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_compr_data_start_addr(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_compr_data_size(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_compr_data_adaptive_1_size(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_compr_data_adaptive_2_size(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_compr_error(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_new_model_addr_used(uint16_t trans_id, uint8_t *cmd);
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int rdcu_read_cmd_samples_used(uint16_t trans_id, uint8_t *cmd);
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/* SRAM EDAC read accessors */
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int rdcu_read_cmd_sram_edac_status(uint16_t trans_id, uint8_t *cmd);
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/* SRAM EDAC write accessors */
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int rdcu_write_cmd_sram_edac_ctrl(uint16_t trans_id, uint8_t *cmd);
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#endif /* RDCU_CMD_H */